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M27V512
512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM
s
LOW VOLTAGE READ OPERATION: 3V to 3.6V FAST ACCESS TIME: 100ns LOW POWER CONSUMPTION: - Active Current 10mA at 5MHz - Standby Current 10A
28 28
s s
s s s
PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIME: 100s/byte (typical) ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 3Dh
1
1
FDIP28W (F)
PDIP28 (B)
DESCRIPTION The M27V512 is a low voltage 512 Kbit EPROM offered in the two ranges UV (ultra viloet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 65,536 by 8 bits. The M27V512 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages. Table 1. Signal Names
A0-A15 Q0-Q7 E GV PP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Supply Voltage Ground
PLCC32 (K)
TSOP28 (N) 8 x 13.4mm
Figure 1. Logic Diagram
VCC
16 A0-A15
8 Q0-Q7
E GVPP
M27V512
VSS
AI00732B
May 1998
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M27V512
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI01907
VSS DU Q3 Q4 Q5
AI00733B
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
1 28 2 27 3 26 4 25 5 24 6 23 7 22 M27V512 8 21 9 20 10 19 11 18 12 17 13 16 14 15
VCC A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3
A6 A5 A4 A3 A2 A1 A0 NC Q0
A7 A12 A15 DU VCC A14 A13 1 32 A8 A9 A11 NC GVPP A10 E Q7 Q6 9 M27V512 25 17 Q1 Q2
Warning: NC = Not Connected, DU = Don't Use
Figure 2C. TSOP Pin Connections
GVPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3
22
21
28 1
M27V512
15 14
7
8
AI00734B
A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2
DEVICE OPERATION The operating modes of the M27V512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature. Read Mode The M27V512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27V512 has a standby mode which reduces the supply current from 10mA to 10A with low voltage operation VCC 3.6V, see Read Mode DC Characteristics table for details.The M27V512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.
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M27V512
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14 Unit C C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V 0.5V.
E VIL VIL VIL Pulse V IH V IH VIL
GV PP V IL VIH VPP VPP X V IL
A9 X X X X X VID
Q0-Q7 Data Out Hi-Z Data In Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 3Dh
Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
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M27V512
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V
Figure 3. Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01822
1N914
3.3k
Standard 2.4V
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supplyconnection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
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M27V512
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 3.3V 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS IOL = 2.1mA IOH = -400A IOH = -100A 2.4 VCC - 0.7V Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz, VCC 3.6V E = VIH E > VCC - 0.2V, VCC 3.6V VPP = VCC -0.3 2 Min Max 10 10 10 1 10 10 0.8 VCC + 1 0.4 Unit A A mA mA A A V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 3.3V 10%; VPP = VCC)
M27V512 Symbol Alt Parameter Test Condition -100 (3) Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 Max 100 100 45 30 30 0 0 0 -120 Min Max 120 120 45 35 35 ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions.
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M27V512
Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C; VCC = 3.3V 10%; VPP = VCC))
M27V512 Symbol Alt Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -150 Max 150 150 50 40 40 0 0 0 -200 Min Max 200 200 60 50 50 ns ns ns ns ns ns Unit
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A15
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ
AI00735B
Programming The M27V512 has been designed to be fully compatible with the M27C512 and has the same electronic signature. As a result the M27V512 can be programmed as the M27C512 on the same programming equipments applying 12.75V on VPP and 6.25V on VCC by the use of the same PRESTO IIB algorithm. When delivered (and after each erasure for UV EPROM), all bits of the M27V512 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ul-
traviolet light (UV EPROM). The M27V512 is in the programming mode when VPP input is at 12.75V and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins.The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V. The M27V512 can use PRESTO IIB Programming Algorithm that drastically reduces the programming time (typically less than 6 seconds). Nevertheless to achieve compatibility with all programming equipments, PRESTO Programming Algorithm can be used as well.
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M27V512
Table 9. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol ILI I CC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -1mA 3.6 11.5 12.5 E = VIL -0.3 2 Test Condition V IL <= VIN <= VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
Table 10. MARGIN MODE AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V
Symbol tA9HVPH tVPHEL tA10HEH tA10LEH tEXA10X t EXVPX tVPXA9X Alt t AS9 tVPS tAS10 tAS10 tAH10 tVPH tAH9 Parameter VA9 High to VPP High VPP High to Chip Enable Low VA10 High to Chip Enable High (Set) VA10 Low to Chip Enable High (Reset) Chip Enable Transition to VA10 Transition Chip Enable Transition to VPP Transition VPP Transition to VA9 Transition Test Condition Min 2 2 1 1 1 2 2 Max Unit s s s s s s s
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
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M27V512
Table 11. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tAVEL tQVEL t VCHEL tVPHEL tVPLVPH tELEH tEHQX tEHVPX tVPLEL tELQV tEHQZ (2) t EHAX Alt tAS tDS tVCS tOES tPRT tPW tDH tOEH tVR tDV tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VCC High to Chip Enable Low VPP High to Chip Enable Low VPP Rise Time Chip Enable Program Pulse Width (Initial) Chip Enable High to Input Transition Chip Enable High to VPP Transition VPP Low to Chip Enable Low Chip Enable Low to Output Valid Chip Enable High to Output Hi-Z Chip Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 50 95 2 2 2 1 130 105 Max Unit s s s s ns s s s s s ns ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested.
Figure 6. MARGIN MODE AC Waveforms
VCC
A8
A9 tA9HVPH GVPP tVPHEL E tA10HEH A10 Set tEXA10X tEXVPX tVPXA9X
A10 Reset tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
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M27V512
Figure 7. Programming and Verify Modes AC Waveforms
A0-A15 tAVEL Q0-Q7 tQVEL VCC tVCHEL GVPP tVPHEL E tELEH PROGRAM DATA IN
VALID tEHAX DATA OUT tEHQX tELQV tEHVPX tEHQZ
tVPLEL
VERIFY
AI00737
Figure 8. Programming Flowchart
VCC = 6.25V, VPP = 12.75V SET MARGIN MODE
n=0
E = 100s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES RESET MARGIN MODE CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V
AI00738B
PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with STMicroelectronics M27V512 due to several design innovations described in the M27V512 datasheet to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 100s program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin. Program Inhibit Programming of multiple M27V512s in parallel with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27V512 may be common. A TTL low level pulse applied to a M27V512's E input, with VPP at 12.75V, will program that M27V512. A high level E input inhibits the other M27V512s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at V IL. Data should be verified with tELQV after the falling edge of E.
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M27V512
On-Board Programming The M27V512 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27V512. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V512. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27V512, these two identifier bytes are given in Table 4 and can be readout on outputs Q0 to Q7. Note that the M27V512 and M27C512 have the same identifier bytes. ERASURE OPERATION (applies for UV EPROM) The erasure characteristics of the M27V512 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27V512 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27V512 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27V512 window to prevent unintentional erasure. The recommended erasure procedure for the M27V512 is exposure to short wave ultraviolet light which has wavelength 2537 A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27V512 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
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M27V512
Table 12. Ordering Information Scheme
Example: Device Type Speed -100 -120 -150 -200 = 100 ns = 120 ns = 150 ns = 200 ns
(1)
M27V512
-100 K
1
TR
Package F = FDIP28W B = PDIP28 K = PLCC32 N = TSOP28: 8 x 13.4mm Temperature Range 1 = -0 to 70 C 6 = -40 to 85 C Optio n TR = Tape & Reel packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M27V512
Table 13. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D E E1 e1 e3 eA L S N 7.11 2.54 33.02 15.40 13.05 - - 16.17 3.18 1.52 - 4 28 0.50 3.90 0.40 1.17 0.22 Min Max 5.71 1.78 5.08 0.55 1.42 0.31 38.10 15.80 13.36 - - 18.32 4.10 2.49 - 15 0.280 0.100 1.300 0.606 0.514 - - 0.637 0.125 0.060 - 4 28 0.020 0.154 0.016 0.046 0.009 Typ Min Max 0.225 0.070 0.200 0.022 0.056 0.012 1.500 0.622 0.526 - - 0.721 0.161 0.098 - 15 inches
Figure 9. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3 A1 B1 B D2 D S
N 1
A L eA eB C
e
E1
E
FDIPW-a
Drawing is not to scale.
12/16
M27V512
Table 14. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 33.02 15.24 1.52 Min - 0.38 3.56 0.38 - 0.20 36.83 - - 13.59 - - 15.24 3.18 1.78 0 28 Max 5.08 - 4.06 0.51 - 0.30 37.34 - - 13.84 - - 17.78 3.43 2.08 10 0.100 0.590 1.300 0.600 0.060 Typ Min - 0.015 0.140 0.015 - 0.008 1.450 - - 0.535 - - 0.600 0.125 0.070 0 28 Max 0.200 - 0.160 0.020 - 0.012 1.470 - - 0.545 - - 0.700 0.135 0.082 10 inches
Figure 10. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2 A1 B1 D S
N
A L eA C
B
e1
E1
1
E
PDIP
Drawing is not to scale.
13/16
M27V512
Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
Symb A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 9 0.10 0.89 1.27 mm Typ Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.004 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
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M27V512
Table 16. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data
mm Symb Typ A A1 A2 B C D D1 E e L N CP 0.55 0.95 0.17 0.10 13.20 11.70 7.90 - 0.50 0 28 0.10 Min Max 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 - 0.70 5 0.022 0.037 0.007 0.004 0.520 0.461 0.311 - 0.020 0 28 0.004 Typ Min Max 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 - 0.028 5 inches
Figure 12. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
A1
L
Drawing is not to scale
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M27V512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1998 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://w ww.st.com
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